I distinctly remember my high school self, wide-eyed, poring over the soft-core Starr report with friends. 我还清楚地记得高中时代的我,睁大了眼睛,和朋友们一起狼吞虎咽地读着《斯塔尔报告》(StarrReport)中那些香艳的内容。
Implementing the synchronization of industrial Ethernet precise clock based on Nios II soft-core 基于NiosⅡ软核的工业以太网精确时钟同步的实现
Design of an Ethernet Interface Based on the Nios Soft-core Processor 基于Nios软核处理器的以太网接口设计
Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules. 详细设计了帧间解码IP软核,包括运动矢量生成模块、预测处理模块和插值模块。
Research and Design of Soft-core IP for AVS Inter Decoder AVS帧间解码IP软核的研究与设计
Implementation of Soft-Core Processor and DDFS Based on FPGA 基于FPGA的软核处理器及DDFS实现
Research and Design of Nios ⅱ Soft-core Processor NiosⅡ软核处理器的研究与设计
NIOS ⅱ soft-core processor is a flexible and efficient embedded processor promoted by Altera Corporation. NIOSⅡ软核处理器是Altera公司推出的一款灵活高效的嵌入式处理器。
A 40Gb/ s switch IP soft-core with self-dependence intellectual property was realized. 形成了具有自主知识产权的40Gb/s交换IP软核。
According to the structure model of data acquisition and processing system connected by Ethernet, the network interface module based on the Nios soft-core system is designed to construct the network data acquisition system. 为构建网络化的数据采集系统,根据数据采集模块与处理控制模块通过以太网相连接的结构模型,设计了基于Nios软核系统的嵌入式以太网网络接口模块。
This paper introduces 8B/ 10B encoding technique, and puts forward a simple and practical realization method of an 8B/ 10B encoder. Furthermore, a versatile soft-core designed with Verilog is presented. 本文介绍了8B/10B编码技术,提出了一种简单、实用的8B/10B编码器的实现方法,并且采用Verilog语言设计了一种通用的软核。
The prototype designs with soft-core processors of Nios II in FPGA, improves the programmability of network processors. 网络处理器芯片原型采用NIOSii软核处理器在FPGA上实现,提高了网络处理器的可编程能力。
This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU. 提出了一种基于FPGA(现场可编程门阵列)和软核CPU的嵌入式系统设计的新方法。
Design and Implementation of Multi-channel Phone-billing-system Based upon NIOS Soft-core CPU 基于NIOS软核CPU技术的多路电话计费系统的设计与实现
With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core. 通过建立SDH芯片验证平台和SDH芯片测试平台,实现IP软核的功能仿真、时序仿真和芯片性能测试。
SOPC includes soft-core or hard-core CPU 、 memory 、 I/ O and programmable logic resource, which has all the advantage of SOC 、 PLD and FPGA. SOPC综合了SOC、PLD和FPGA的优点,集成了硬核或软核CPU、存储器、I/O以及可编程逻辑。
Nios II soft-core processor implanted into FPGA as the control chip controls and preprocesses the data of the entire image acquisition system. 采用FPGA作为控制芯片,在其中植入NiosⅡ软核处理器以对整个图像采集系统的数据进行控制和预处理。
First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4. 先对灰度量化算法进行了分析和仿真比较,然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。
In practice, the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions. 在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现,或者快速搭建现场总线通信系统,实现灵活的CAN总线接口方案。
First, use of the system functions on a single chip design ideas, using a high-performance soft-core processor ( Nios II CPU) and IP multiplexing and improve the whole system to further improve the speed and flexibility. 第一,运用了在单芯片上实现系统功能的设计思想,采用了高性能的软核处理器(NiosIICPU)和IP复用技术,提高了整个系统的运行速度和进一步改进的灵活性。
It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic. 它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。
The paper introduces the structural features of the network processor Nios II and customized instructions and design methods for forwarding software of the network processor based on the Nios II soft-core processor and design methods for the DSP processor used for the processing of the video and image data. 文中介绍了网络处理器NIOSii的结构特点和自定义指令以及基于NIOSii软核处理器的网络处理器转发软件的设计方法和基于视频图像处理的DSP处理器的设计方法。
The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task. 通过使用SOPC技术,在FPGA内部构建了NIOSⅡ软核处理器,并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统,从而实现了对系统任务的调度。
The Nios ⅱ soft-core processor improve the integration of the system and is helpful to the miniaturization of instrument. NiosⅡ软核处理器提高了系统的集成度,有利于系统的小型化,降低了成本。
The hierarchical, modular design idea was used in the system which embeds the Nios II soft-core processor system in FPGA. And the on-chip hardware and software designs are completed. 整个系统采用层次化、模块化的设计思想,将NIOSii软核处理器系统嵌入到FPGA中,完成片上硬件和软件的设计。
For the digital part, this design is mean to construct the SOPC system in the FPGA, embedded Nios II soft-core processor to control the operation of the entire system. 对于数字部分,在FPGA内构建SOPC系统,嵌入NIOSii软核处理器对整个系统进行控制。
To solute the problem, the idea of kernel hardware design has been put forward. System architecture is divided into soft-core and hardcore. Hardcore will manage application tasks as a coprocessor to improve the real time of system. 针对实时性问题,提出将内核硬件化设计的思想,将系统的体系结构划分为软核和硬核,硬核作为协处理器管理应用任务,提高系统的实时性,使系统的性能得到明显的提高。
Then, through the embedded soft-core processor technology based on FPGA, entire system the control, and processing and transmission of data of were achieved by using the co-design approach of hardware and software. 然后,通过基于FPGA的嵌入式软核处理器技术,采用软硬件协同设计的方法,实现对整个系统功能的控制及数据的处理与发送。